Method and apparatus of tool matching for a semiconductor manufacturing process

ABSTRACT

The present invention provides a method of tool matching for a semiconductor manufacturing process having a first and second path completed by serial combinations of tools for processing of wafers. The method comprises the steps of providing a target value, obtaining a first and second test result of the wafers processed through the first and second path respectively, calculating differences between the first and second test result and the target value to obtain a first and second estimate respectively, and selecting one of the first and second paths according to the estimates.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to a method and apparatus of toolmatching for a semiconductor manufacturing process.

[0003] 2. Description of the Prior Art

[0004] One of the critical factors for success of mass production isyield, defined as the proportion of the number of qualified products tothe total number of products. In semiconductor manufacturing, theproducts are wafers or chips, and the corresponding wafer yield and chipyield are significant. Improvement of the wafer and chip yield reducesthe cost and increases production efficiency since most of the wafers orchips are qualified and few are wasted. Therefore, manufacturingengineers are dedicated to the improvement of yield.

[0005] Conventionally, for improvement of the yield, engineers choose,from the available tools for each one step or operation in themanufacturing process of a product, the one in the best condition.However, the combination of the selected tools is only a possibly butnot absolutely optimized path since the tools are selected individuallyfor each step and correlation between the tools is ignored.

SUMMARY OF THE INVENTION

[0006] Therefore, the object of the present invention is to provide amethod and apparatus of tool matching for a semiconductor manufacturingprocess, wherein the correlation between the tools is taken into accountso that an absolutely optimized path is provided.

[0007] The present invention provides a method of tool matching for asemiconductor manufacturing process having a first and second pathcompleted by serial combinations of tools for processing of wafers. Themethod comprises the steps of providing a target value, obtaining afirst and second test result of the wafers processed through the firstand second path respectively, calculating differences between the firstand second test result and the target value to obtain a first and secondestimate respectively, and selecting one of the first and second pathaccording to the estimates.

[0008] The present invention also provides a method of tool matching fora semiconductor manufacturing process having a plurality of pathscompleted by serial combinations of tools for processing of lots ofwafers. The method comprises the steps of providing a target value T,obtaining groups of test results of lots of wafers processed through thepaths, calculating a mean value and variation of each group of the testresults, wherein the mean value and variation of lot j of the wafersprocessed through path i are W(i,j) and σ(i,j) respectively, providingweights for the lots of the wafers, wherein the weight for lot j of thewafers processed through path i is R(i,j), calculating estimates P ofthe paths, wherein the estimate of path i using the wafers from M0_(th)to Mc_(th) lot is${{P(i)} = {\sum\limits_{j = m_{o}}^{j = m_{c}}{{R\left( {i,j} \right)}\left\lbrack {{{{W\left( {i,j} \right)} - T}} + {\sigma \left( {i,j} \right)}} \right\rbrack}}},$

[0009] and selecting one of the paths according to the estimates.

[0010] The present invention further provides an apparatus of toolmatching for a semiconductor manufacturing process having a first andsecond path completed by serial combinations of tools for processing ofwafers. The apparatus comprises means for providing a target value,means for obtaining a first and second test result of the wafersprocessed through the first and second path respectively, means forcalculating differences between the first and second test result and thetarget value to obtain a first and second estimate respectively, andmeans for selecting one of the first and second path according to theestimates.

BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The following detailed description, given by way of example andnot intended to limit the invention solely to the embodiments describedherein, will best be understood in conjunction with the accompanyingdrawings, in which:

[0012]FIG. 1 is a block diagram showing an apparatus of tool matchingfor a semiconductor manufacturing process according to one embodiment ofthe invention.

[0013]FIG. 2 is a flow chart showing a method of tool matching for asemiconductor manufacturing process according to one embodiment of theinvention.

DETAILED DESCRIPTION OF THE INVENTION

[0014] In the embodiment of the invention will be described in thefollowing, a manufacturing process comprises four steps S1, S2, S3 andS4. The available tools for the step S1, S2, S3 and S4 are TL(1,1),TL(1,2) and TL(2,1), TL(2,2), TL(2,3), TL(2,4) and TL(3,1), TL(3,2) andTL(4,1), TL(4,2), TL(4,3) respectively. Thus there are 48(2×4×2×3) pathsL available.

[0015]FIG. 1 is a block diagram showing an apparatus of tool matchingfor a semiconductor manufacturing process according to one embodiment ofthe invention.

[0016] A wafer acceptance tester 13 carries out wafer acceptance testsof lots of wafers processed through the 48 paths L. A group of testresults for each one lot of wafers is obtained. The storage device 12stores the test results of the lots of the wafers indexed to thecorresponding paths through which the wafers are processed.

[0017] A processing device 11 obtains the test results from the storagedevice 12 and calculates a mean value W and a variation σ of the testresults for each lot of the wafers. A weight R is also provided by theprocessing device 11 for each lot. The weights R are obtained byExponential Weighting Moving Average based on the lots. The storagedevice 12 also stores each of the mean values W and variations σ.

[0018] A target value T is provided and sent to the processing device11. The target value T is the expected value of the test result of theprocessed wafer.

[0019] Then, an estimate P for each path L is calculated by theprocessing device 11. The estimate P(i) of path i L(i) is${\sum\limits_{j = m_{o}}^{j = m_{c}}{R{\left( {i,j} \right)\left\lbrack {{{{W\left( {i,j} \right)} - T}} + {\sigma \left( {i,j} \right)}} \right\rbrack}}},$

[0020] wherein j is the order of the lots processed through the pathL(i), Mc is the last lot, M0 is the first lot, R(i,j) is the weight oflot j processed through the path L(i), W(i,j) is the mean value of thetest results of lot j processed through the path L(i) and σ(i,j) is thevariation of the test results of lot j processed through the path L(i).

[0021] Finally, the estimates P of the paths L appear on the display 14.The engineers select one path with the smallest estimate, which is theprior choice for accomplishment of the target value.

[0022] Additionally, the wafer acceptance tester 13 carries on the testsof the following lots of the wafers so that there are more test resultsstored in the storage device 12 and the estimates P of the paths L arecontinually updated.

[0023] In the embodiment, the difference [|W(i,j)−T|] and the variationσ(i,j) have an equal weight. However, they may have different weights k1and k2 for a special estimation, that is to say, the estimate P(i) ofpath i L(i) is$\sum\limits_{j = m_{o}}^{j = m_{c}}{{{R\left( {i,j} \right)}\left\lbrack {{{k1}{{{W\left( {i,j} \right)} - T}}} + {{k2}\quad {\sigma \left( {i,j} \right)}}} \right\rbrack}.}$

[0024] . Further, the weight R(i,j) is a time-dependent parameter andincreases with the order of the lot.

[0025]FIG. 2 is a flow chart showing a method of tool matching for asemiconductor manufacturing process according to one embodiment of theinvention.

[0026] In the embodiment of the invention described here, amanufacturing process comprises four steps S1, S2, S3 and S4. Theavailable tools for the step S1, S2, S3 and S4 are TL(1,1), TL(1,2) andTL(2,1), TL(2,2), TL(2,3), TL(2,4) and TL(3,1), TL(3,2) and TL(4,1),TL(4,2), TL(4,3) respectively. Thus there are 48(2×4×2×3) paths Lavailable.

[0027] In step 21, wafer acceptance tests of lots of wafers processedthrough the 48 paths L are carried out. A group of test results for eachlot of wafers is obtained. The test results of the lots of the wafersindexed to the corresponding paths through which the wafers areprocessed are stored.

[0028] In step 22, a mean value W and a variation a of the test resultsfor each lot of the wafers are obtained. A weight R is also provided foreach lot. The weights R are obtained by Exponential Weighting MovingAverage based on the lots. Each of the mean values W and variations σare also stored.

[0029] In step 23, A target value T is provided, which is the expectedvalue of the test result of the processed wafer.

[0030] In step 24, an estimate P for each path L is calculated. Theestimate P(i) of path i L(i) is${\sum\limits_{j = m_{o}}^{j = m_{c}}{R{\left( {i,j} \right)\left\lbrack {{{{W\left( {i,j} \right)} - T}} + {\sigma \left( {i,j} \right)}} \right\rbrack}}},$

[0031] wherein j is the order of the lots processed through the pathL(i), Mc is the last lot, M0 is the first lot, R(i,j) is the weight oflot j processed through the path L(i), W(i,j) is the mean value of thetest results of lot j processed through the path L(i) and σ(i,j) is thevariation of the test results of lot j processed through the path L(i).

[0032] Finally, in step 25, the estimates P of the paths L are listed.The engineers select one path with the smallest estimate, which is theprior choice for accomplishment of the target value.

[0033] Additionally, the tests of the following lots of the wafers arecarried out so that there are more test results generated and theestimates P of the paths L are continually updated.

[0034] In conclusion, the present invention provides a tool matchingmethod wherein the wafer acceptance test results are stored in acontinually updated database, a weight is assigned to each lot of thewafers and the performances of the available paths are statisticallyestimated using the database. Thus, a quantified estimate is providedfor tool matching for a semiconductor manufacturing process.

[0035] While the invention has been described by way of example and interms of the preferred embodiment, it is to be understood that theinvention is not limited to the disclosed embodiments. On the contrary,it is intended to cover various modifications and similar arrangementsas would be apparent to those skilled in the art. Therefore, the scopeof the appended claims should be accorded the broadest interpretation soas to encompass all such modifications and similar arrangements.

What is claimed is:
 1. A method of tool matching for a semiconductor manufacturing process having a first and second path completed by serial combinations of tools for processing of wafers, the method comprising the steps of: providing a target value; obtaining a first and second test result of the wafers processed through the first and second path respectively; calculating differences between the first and second test result and the target value to obtain a first and second estimate respectively; and selecting one of the first and second path according to the estimates.
 2. The method as claimed in claim 1 wherein the first test result is a mean value of results obtained by carrying out a wafer acceptance test of a lot of the wafers processed through the first path.
 3. The method as claimed in claim 1 wherein the second test result is a mean value of results obtained by carrying out a wafer acceptance test of a lot of the wafers processed through the second path.
 4. The method as claimed in claim 1 further comprising the steps of: obtaining variations of the first and second test result; and calculating sums of the differences from the target value and variations of the first and second test result to obtain the first and second estimates.
 5. The method as claimed in claim 4 wherein the first test result and the variation thereof are respectively a mean value and a variation of results obtained by carrying out a wafer acceptance test of a lot of the wafers processed through the first path.
 6. The method as claimed in claim 4 wherein the second test result and the variation thereof are respectively a mean value and a variation of results obtained by carrying out a wafer acceptance test of a lot of the wafers processed through the second path.
 7. The method as claimed in claim 4 wherein differences and variations have different weights.
 8. The method as claimed in claim 1 further comprising the steps of: obtaining a third and fourth test result of the first and second path respectively; providing a first, second, third and fourth weight of the first, second, third and fourth test result respectively; and calculating sums of the products of the weights and the differences between the test results and the target value to obtain the first and second estimates.
 9. The method as claimed in claim 8 wherein the weights are time-dependent parameters and increase with an order of lots of the wafers.
 10. The method as claimed in claim 1 wherein one of the first and second path with the smaller estimate is a prior choice for accomplishment of the target value.
 11. A method of tool matching for a semiconductor manufacturing process having a plurality of paths completed by serial combinations of tools for processing of lots of wafers, the method comprising the steps of: providing a target value T; obtaining groups of test results of lots of wafers processed through the paths; calculating a mean value and variation of each group of the test results, wherein the mean value and variation of lot j of the wafers processed through path i are W(i,j) and σ(i,j) respectively; providing weights for the lots of the wafers, wherein the weight for lot j of the wafers processed through path i is R(i,j); calculating estimates P of the paths, wherein the estimate of path i using the wafers from M0_(th) to Mc_(th) lot is ${{P(i)} = {\sum\limits_{j = m_{o}}^{j = m_{c}}{{R\left( {i,j} \right)}\left\lbrack {{{{W\left( {i,j} \right)} - T}} + {\sigma \left( {i,j} \right)}} \right\rbrack}}};$

and selecting one of the paths according to the estimates.
 12. The method as claimed in claim 11 further comprises the steps of: providing weights k1 and k2; and calculating estimates P of the paths, wherein the estimate of path i using the wafers from M0_(th) to Mc_(th) lot is ${P(i)} = {\sum\limits_{j = m_{o}}^{j = m_{c}}{{{R\left( {i,j} \right)}\left\lbrack {{{k1}{{{W\left( {i,j} \right)} - T}}} + {{k2}\quad {\sigma \left( {i,j} \right)}}} \right\rbrack}.}}$

.
 13. The method as claimed in claim 11 wherein the weights R(i,j) increase with an order of the lots of the wafers.
 14. An apparatus of tool matching for a semiconductor manufacturing process having a first and second path completed by serial combinations of tools for processing of wafers, the apparatus comprising: means for providing a target value; means for obtaining a first and second test result of the wafers processed through the first and second path respectively; means for calculating differences between the first and second test result and the target value to obtain a first and second estimate respectively; and means for selecting one of the first and second path according to the estimates. 